On-board Hardware and S/W Development
In Orbit
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HEPI — INTEGRAL instrument hardware (FPGA/ASIC) 1996–1998
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Role — hardware design and development, submitted as a diploma thesis
Goal — turn the raw photon stream of IBIS into usable science data by preprocessing every detected event on board.
Implementation — HEPI, an ASIC developed at the University of Tübingen for the gamma-ray imaging instrument aboard ESA’s INTEGRAL satellite.
IBIS observes with two detector planes — ISGRI, a cadmium telluride detector optimised for lower energies, and PICsIT, a caesium iodide scintillator detector for higher energies — covering roughly 15 keV to 10 MeV. HEPI interfaces with both planes, processing individual photon events, synchronising their timing and identifying coincident events — used to reconstruct photon interactions and improve background rejection.
During the engineering phase the design ran on FPGAs, allowing the logic to be tested and revised before it was committed to the fixed ASIC. The full development is documented in the diploma thesis (in German), submitted in 1998.
Term Meaning HEPI Hardware Event Preprocessor for IBIS IBIS Imager on Board the INTEGRAL Satellite INTEGRAL International Gamma-Ray Astrophysics Laboratory ISGRI INTEGRAL Soft Gamma-Ray Imager PICsIT PIxellated CsI Telescope ASIC Application-Specific Integrated Circuit FPGA Field-Programmable Gate Array keV/MeV kilo-/mega-electronvolt (photon energy) 
HEPI -
IASW — INTEGRAL instrument software (Ada) 2002–2009
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Role — Team Lead, software developer
Goal — command and monitor the IBIS instrument aboard INTEGRAL and process its science data on board.
Challenge — the software runs on the DPE, a radiation-tolerant 1750A processor clocked at 13 MHz with only 2 MB of memory.
Implementation — IASW, developed at the University of Tübingen, runs priority-controlled tasks under CSSW, a preemptive multitasking operating system shared by all INTEGRAL instruments. Besides handling telecommands and housekeeping, most of the processing effort goes into fetching and compressing histogram blocks and evaluating the single-photon events supplied by HEPI — applying loss-free compression, rejecting out-of-view Compton events and distributing the limited telemetry rate between data types according to their priority.
Fun fact — our team found a bug in TLD’s certified Ada compiler, virtually unheard of for a certified compiler: an edge case in memory management on this particular hardware.
Term Meaning IASW Instrument Application Software CSSW Common System Software IBIS Imager on Board the INTEGRAL Satellite INTEGRAL International Gamma-Ray Astrophysics Laboratory DPE Data Processing Electronics 1750A MIL-STD-1750A processor architecture HEPI Hardware Event Preprocessor for IBIS TLD certified Ada compiler vendor Ada programming language 
DPE -
CDMU — XMM-Newton main computer patch (Ada) 2017
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Role — sole Ada developer
Goal — enable the MTR aboard XMM-Newton by allowing the hydrazine to be cooled to the lower B-Side temperature limits.
Challenge — reaching those limits means switching off the A-Side hardware LTP, deliberately sacrificing a layer of hardware redundancy — justified only because the alternative is an even higher risk, and only when compensated as far as possible by other means such as procedures, monitoring and software patches.
Implementation — a CDMU software patch, applied in orbit, extends the existing TDC/TCL patch to protect the state of the HLCLs in software, partly compensating for the reduced hardware redundancy.
Term Meaning MTR Main Tank Replenishment CDMU Central Data Management Unit HLCL Heater Latching Current Limiter LTP Low-Temperature Protection HTP High-Temperature Protection TDC Thermal Duty Cycle TCL Thermal Control Loop Ada programming language MCR Main Control Room















